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ISL5216
INSTRUCTION BIT FIELDS (Continued)
BIT
POSITIONS
63
FUNCTION
Reserved
Set to 0.
DESCRIPTION
66:64
Coefficient Memory
Block Size
66:64
0
1
2
3
4
5
6
7
Memory Block Size
8
16
32
64
128
256
512
1024
(Modulo addressing can be used, but is usually not needed. If not needed this bit field can always be
set to 7).
75:67
84:76
93:85
95:94
104:96
Number of FIR
Outputs
Read Address
Pointer Step
Initial Address Offset
Reserved
Memory Reads Per
Number of FIR outputs (range is 1 to 512, load w/ desired value minus 1).
This is usually equal to the total decimation that follows the filter.
Read address pointer step (for next run). This is usually equal to the filter decimation times the number
of outputs from the instruction.
Initial address offset (to ADDRB). This is the offset from the start address to other end of filter.
For symmetric filters, usually equal to -1 x (number of taps -1).
Set to 0
This is based on the number of taps (load with value below minus 1).
FIR Output
Type
Symmetric, even number of taps
Symmetric, odd number of taps
Decimating HBF
Asymmetric
Complex
Resampling
Interpolating HBF
Value
(taps/2) or floor((taps+1)/2).
(taps+1)/2 or floor((taps+1)/2).
(taps+5)/4.
taps.
taps .
taps/phase (six taps per phase for the ROM’d coefficients provided).
(taps+5)/4-1 .
106:105
115:107
117:116
119:118
122:120
Clocks Per
Memory Read
Data Memory
Step Size 1
Data Memory
Step Size 2
Data Memory
Address Offset Step
Coefficient Memory
Step Size
Set to 0 for all but complex FIR, which is set to 1.
(ADDRA) Step size for all but the last tap computation of the FIR.
Set to -2 for HBF, -1 otherwise.
(ADDRA) Step size for last tap computation. Set to -1.
117:116 Step size
0
0
1
-1
2
-2
3
step size value.
(ADDRB) Step size for opposite end of symmetric filter. Set to +2 for Decimating HBF, to +1 for others
(the B data is not used for asymmetric, resampling, and complex filters).
(ADDRC) Usually set to 1.
122:120 Step size
21
0
1
2
3
4
5
6
7
0
1
2
4
8
16
32
64
FN6013.3
July 13, 2007
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